29W040 datasheet(16/31 Pages) STMICROELECTRONICS

16 / 31 page

Symbol

Alt

Parameter

M29W040

Unit

-100

-120

VCC = 3.3V

±0.3V

CL = 30pF

VCC = 3.3V

±0.3V

Min

Max

Min

Max

tAVAV

tWC

Address Valid to Next Address Valid

100

120

tWLEL

tWS

Write Enable Low to Chip Enable Low

tELEH

tCP

Chip Enable Low to Chip Enable High

tDVEH

tDS

Input Valid to Chip Enable High

tEHDX

tDH

Chip Enable High to Input Transition

tEHWH

tWH

Chip Enable High to Write Enable High

tEHEL

tCPH

Chip Enable High to Chip Enable Low

tAVEL

tAS

Address Valid to Chip Enable Low

tELAX

tAH

Chip Enable Low to Address Transition

tGHEL

Output Enable High Chip Enable Low

tVCHWL

tVCS

VCC High to Write Enable Low

µs

tEHQV1

(1)

Chip Enable High to Output Valid (Program)

µs

tEHQV2

(1)

Chip Enable High to Output Valid

(Block Erase)

1.5

sec

tEHGL

tOEH

Chip Enable High to Output Enable Low

Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV =tWHQ7V +tQ7VQV.

Table 14A. Write AC Characteristics, Chip Enable Controlled

(TA = 0 to 70

°C, –20 to 85°C or –40 to 85°C)

Power Up

The memory Command Interface is reset on power

up to Read Array. Either E or W must be tied to VIH

during Power-up to allow maximum security and

the possibility to write a command on the first rising

adge of E or W. Any write cycle initiation is blocked

when VCC is below VLKO.

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling, each device in a system should

have the VCC rail decoupledwith a 1.0

µF capacitor

close to the VCC and VSS pins. The PCB trace

widths should be sufficient to carry the VCC pro-

gram and erase currents required.

16/31

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