M48T86PC datasheet(5/23 Pages) STMICROELECTRONICS

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M48T86

RST (Reset Input). The M48T86 is reset when

the RST input is pulled low. With a valid VCC ap-

plied and a low on RST, the following events oc-

cur:

1. Periodic Interrupt Enable (PIE) bit is cleared to

a zero. (Register B; Bit 6)

2. Alarm Interrupt Enable (AIE) bit is cleared to a

zero.(Register B; bit 5)

3. Update Ended Interrupt Request (UF) bit is

cleared to a zero. (Register C; Bit 4)

4. Interrupt Request (IRQF) bit is cleared to a zero.

(Register C Bit 7)

5. Periodic Interrupt Flag (PF) bit is cleared to a

zero. (Register C; Bit 6)

6. The device is not accessible until RST is re-

turned high.

7. Alarm Interrupt Flag (AF) bit is cleared to a zero.

(Register C; Bit 5)

8. The IRQ pin is in the high impedance state.

9. Square Wave Output Enable (SQWE) bit is

cleared to zero. (Register B; Bit 3).

10.Update Ended Interrupt Enable (UIE) is cleared

to a zero. (Register B; Bit 4)

RCL (RAM Clear). The RCL pin is used to clear

all 114 storage bytes, excluding clock and control

registers, of the array to FF(hex) value. The array

will be cleared when the RCL pin is held low for at

least 100ms with the oscillator running. Usage of

this pin does not affect battery load. This function

is applicable only when VCC is applied.

R/W (Read/Write Input). The R/W pin is utilized

to latch data into the M48T86 and provides func-

tionality similar to W in other memory systems.

ADDRESS MAP

The address map of the M48T86 is shown in Fig-

ure 9. It consists of 114 bytes of user RAM, 10

bytes of RAM that contain the RTC time, calendar

and alarm data, and 4 bytes which are used for

control and status. All bytes can be read or written

to except for the following:

1. Registers C & D are read-only.

2. Bit 7 of Register A is read-only.

The contents of the four Registers A, B, C, and D

are described in the "Registers" section.

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