M48T201V datasheet(11/33 Pages) STMICROELECTRONICS

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M48T201Y, M48T201V

WRITE Mode

The M48T201Y/V is in the WRITE Mode whenever

W (WRITE Enable) and E (Chip Enable) are low

state after the address inputs are stable. The start

of a WRITE is referenced from the latter occurring

falling edge of W or E. A WRITE is terminated by

the earlier rising edge of W or E. The addresses

must be held valid throughout the cycle. E or W

must return high for a minimum of tEHAX from Chip

Enable or tWHAX from WRITE Enable prior to the

initiation of another READ or WRITE Cycle. Data-

in must be valid tDVWH prior to the end of WRITE

and remain valid for tWHDX afterward. G should be

kept high during WRITE Cycles to avoid bus con-

tention; although, if the output bus has been acti-

vated by a low on E and G a low on W will disable

the outputs tWLQZ after W falls.

When

the

address value

presented to the

M48T201Y/V during the WRITE is in the range of

7FFFFh-7FFF0h, one of the on-board TIME-

KEEPER® registers will be selected and data will

be written into the device. When the address value

presented to M48T201Y/V is outside the range of

TIMEKEEPER registers, an external SRAM loca-

tion is selected.

Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals

AI02336

GCON

DQ0-DQ7

ECON

DATA IN

VALID

ADDRESS

tAVAV

tAVEH

tAVAV

WRITE

READ

DATA OUT

VALID

DATA OUT

VALID

tAVWH

tAVQV

tWLWH

tWHDX

tWHAX

tWHQX

tEPD

tRO

tWLQZ

tDVWH

tGLQV

tEHQZ

tDVEH

DATA IN

VALID

tELEH

tEHAX

tAVEL

tEHDX

tAVWL

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