AI02589

18

A0-A17

EE

DQ0-DQ7

VCC

M39208

G

EF

VSS

8

W

Figure 1. Logic Diagram

M39208

Single Chip 2 Mbit Flash and 64 Kbit Parallel EEPROM Memory

PRELIMINARY DATA

2.7V to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPARATIONS

100ns ACCESS TIME

(Flash and EEPROM blocks)

WRITE, PROGRAM and ERASE STATUS BITS

CONCURRENT MODE (Read Flash while

writing to EEPROM)

100,000 ERASE/WRITE CYCLES

10 YEARS DATA RETENTION

LOW POWER CONSUMPTION

– Stand-by mode: 60

µA

– Automatic Stand-by mode

– Deep Power Down mode

64 bytes ONE TIME PROGRAMMABLE

MEMORY

STANDARD EPROM/OTP MEMORY

PACKAGE

EXTENDED TEMPERATURE RANGES

DESCRIPTION

The M39208 is a memory device combining Flash

and EEPROM into a single chip and using single

supply voltage. The memory is mapped in two

blocks: 2 Mbit of Flash memory and 64 Kbit of

EEPROM memory. Each space is independant for

writing, in concurrent mode the Flash Memory can

be read while the EEPROM is being written.

A0-A17

Address Inputs

DQ0-DQ7

Data Input / Outputs

EE

EEPROM Block Enable

EF

Flash Block Enable

G

Output Enable

W

Write Enable

Supply Voltage

Ground

Table 1. Signal Names

TSOP32 (NA)

8 x 20 mm

February 1999

1/30

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

TSOP32 (NB)

8 x 14 mm