MSC8103SLASHD datasheet(30/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

1-26

Freescale Semiconductor

Signals/Connections

PC28

BRG4O

CLK4

TIN1

Timer2: TOUT2

SCC2: CTS, CLSN

Output

Input

Output

Input

Baud-Rate Generator 4 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

Clock 4

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

Timer Input 1

A timer can have one of the following sources: another timer, system

clock, system clock divided by 16 or a timer input. The CPM supports up to

4 timer inputs. The timer inputs can be captured on the rising, falling or

both edges.

Timer 2: Timer Output 2

The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4])

when the reference value is reached. This signal can be an active-low

pulse or a toggle of the current output. The output can also be connected

internally to the input of another timer, resulting in a 32-bit timer.

SCC2: Clear to Send, Collision

Typically used in conjunction with RTS. The MSC8103 SCC2 transmitter

sends out a request to send data signal (RTS). The request is accepted

when CTS is returned low. CLSN is the signal used in Ethernet mode. See

also PC13.

PC27

BRG5O

CLK5

TIMER3/4: TGATE2

Output

Input

Baud-Rate Generator 5 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

Clock 5

When selected, CLK5 is a source for the SIU timers via BRG1O. See the

System Interface Unit (SIU) chapter in the MSC8103 Reference Manual

for additional information. If CLK5 is not enabled, BRG1O uses an internal

input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU

timers is disabled.

Timer 3/4: Timer Gate 2

The timers can be gated/restarted by an external gate signal. There are

two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls

timer 3 and/or 4.

Table 1-9.

Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

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