| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
M29F016D bảng dữ liệu(PDF) 5 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
M29F016D bảng dữ liệu(HTML) 5 Page - STMicroelectronics |
|
5 / 37 page ![]() Obsolete Product(s) - Obsolete Product(s) 5/37 M29F016D SUMMARY DESCRIPTION The M29F016D is a 16 Mbit (2Mb x8) non-volatile memory that can be read, erased and repro- grammed. These operations can be performed us- ing a single low voltage 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into 32 uniform blocks of 64Kbytes (see Figure 5, Block Addresses) that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected in groups of 4 to prevent accidental Program or Erase commands from modifying the memory. Program and Erase com- mands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special op- erations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identi- fied. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. They allow simple connection to most micropro- cessors, often without additional logic. The memory is offered in TSOP40 (10 x 20mm) and SO44 packages. Access times of 55, 70 and 90ns are available. In order to meet environmental requirements, ST offers the M29F016D in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum rat- ings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK speci- fications are available at: www.st.com. The memory is supplied with all the bits erased (set to ’1’). Figure 2. Logic Diagram Table 1. Signal Names AI05269 21 A0-A20 W DQ0-DQ7 VCC M29F016D E VSS 8 G RP RB A0-A20 Address Inputs DQ0-DQ7 Data Inputs/Outputs E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output VCC Supply Voltage VSS Ground NC Not Connected Internally |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |