TS4962M datasheet(38/41 Pages) STMICROELECTRONICS

38 / 41 page

Package information

TS4962M

38/41

Package information

In order to meet environmental requirements, STMicroelectronics offers these devices in

ECOPACK® packages. These packages have a lead-free second level interconnect. The

category of second level interconnect is marked on the package and on the inner box label,

in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics

trademark. ECOPACK specifications are available at: www.st.com.

Figure 72.

Pin-out for 9-bump flip-chip (top view)

Figure 73.

Marking for 9-bump flip-chip (top view)

Figure 74.

Mechanical data for 9-bump flip-chip

1/A1

7/C1

8/C2

9/C3

4/B1

6/B3

2/A2

3/A3

5/B2

GND

STBY

GND

OUT

1/A1

7/C1

8/C2

9/C3

4/B1

6/B3

2/A2

3/A3

5/B2

GND

STBY

GND

OUT

■ Bumps are underneath

■ Bump diameter = 300

μm

■ ST Logo

■ Symbol for lead-free: E

■ Two first XX product code: 62

■ third X: Assembly code

■ Three digits date code: Y for year - WW for week

■ The dot is for marking pin A1

XXX

YWW

XXX

YWW

■

Die size: 1.6mm x 1.6mm

±30μm

■

Die height (including bumps): 600

μm

■

Bump diameter: 315

μm ±50μm

■

Bump diameter before reflow: 300

μm ±10μm

■

Bump height: 250

μm ±40μm

■

Die height: 350

μm ±20μm

■

Pitch: 500

μm ±50μm

■

Coplanarity: 50

μm max

1.60 mm

0.5mm

∅ 0.25mm

1.60 mm

0.5mm

∅ 0.25mm

600µm

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