RESET

tD_HL

tD

VIT- + VHYS

VPOR

tSTRT + tD

Unde ned

VDD

VDD(MIN)

VIT-

tD

tD_HL

Unde ned

A.

Open-Drain timing diagram assumes the RESET / RESET pin is connected via an external pull-up resistor to VDD.

B.

tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed

time will be added to the startup time, VDD slew rate = 1V / µs.

C.

Be advised that the VDD falling slew rate is (slew rate > 1V / µs) and resulting RESETin what is shown above figure. The RESET

behavior would be similar to Figure 6-1 if the slew rate was much slower or if VDD decay time is larger than the prop delay (tD_HL).

Figure 6-3. Timing Diagram for TLV841CxxL (CT) Active Low Output

[Open-Drain and Push-Pull Output Topology]

VIT+

tP_HL

VHYS

VIT-

tD

VIT+

VHYS

VIT-

tMR_tD

VMR_L

Time

tMR_RES

tMR_PW

(1)

MR

VDD

RESET

VMR_H

(2)

(1) MR pulse width too small to assert RESET

(2) MR voltage not low enough to assert RESET

A.

Open-Drain timing diagram assumes the RESET / RESET pin is connected via an external pull-up resistor to VDD.

Figure 6-4. Timing Diagram for TLV841MxxL Active Low Output (MR)

[Open-Drain and Push-Pull Output Topology]

TLV841

SLVSFO5E – APRIL 2020 – REVISED FEBRUARY 2026

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