MP2617BGL datasheet(29/33 Pages) MPS

29 / 33 page

MP2617A, MP2617B

– SINGLE CELL SWITCHING CHARGER WITH POWER PATH

MP2617A, MP2617B Rev. 1.25

www.MonolithicPower.com

8/14/2020

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

When SYSFB is programmed using external

resistors, the control loop function is changed.

A zero point is added around the cross over

frequency of the DC gain, and this may result in

the phase margin varied a lot, which may cause

the unstable operation. To avoid this condition,

a minimum capacitance requirement should be

satisfied to make the pole point to compensate

the zero point. This minimum capacitance is

20uF for a general application.

So, for the SYSFB programmed condition, the

CSYS should be selected as max (CSYS_MIN,

20uF), CSYS_MIN is calculated from the formula of

equation (13), as shown in Table 5. For better

stability

margin,

select

47uF

ceramic

capacitor with 6.3V and above voltage rating as

the output capacitor in this case.

Resistor Choose for NTC Sensor

According to formulas in “Battery Temperature

Monitor

”, the low and high temperature

threshold ratio of MP2625B is 65% and 33.5%,

so we can get the following:

NTC_LOW

NTC_HIGH

R //R

=65%

(14)

R +R //R

R //R

=33.5%

(15)

R +R //R

The two resistors RT1 and RT2 allow the high

temperature limit and low temperature limit to

programmed

independently.

With

this

feature, MP2617A and MP2617B can fit most

type of NTC thermistors and different operation

temperature range requirement.

RT1 and RT2 can be calculated according to

different type of NTC thermistor, operation

temperature range and equation (14) and (15).

We also provide calculation tool for convenient

design.

For example, if the thermistor NCP18XH103 is

selected, and the application requires 0oC to

50oC operation temperature range. Check the

datasheet of NCP18XH103 to get the following

information:

At 0oC, the RNTC_LOW=27.219kΩ

At 50oC, the RNTC_HIGH=4.161kΩ

Using

the

calculation

tool

calculate

RT1=7.11kΩ and RT2= 25.61kΩ. Then select the

most closing 1% accuracy resistance for RT1

and RT2.

PCB Layout Guideline

It is important to pay special attention to the

PCB layout to meet specified noise, efficiency

and stability requirements. The following design

considerations can improve circuit performance:

1) Route the power stage adjacent to their

grounds.

Aim

minimize

the

high-side

switching node (SW, inductor), trace lengths in

the high-current paths and the current sense

resistor trace.

Keep the switching node short and away from

all small control signals, especially the feedback

network.

Place the input capacitor as close as possible

to the IN and PGND pins.

Place the output inductor close to the IC and

connect the output capacitor between the

inductor and PGND of the IC.

2) For high-current applications, the balls for the

power pads (IN, SW, SYS, BATT and PGND)

should be connected to as much copper in the

board as possible. This improves thermal

performance because the board conducts heat

away from the IC.

3) The PCB should have a ground plane

connected

directly

the

return

all

components

through

vias

(two

vias

per

capacitor for power-stage capacitors, one via

per capacitor for small-signal components). It is

also recommended to put vias inside the PGND

pads for the IC, if possible. A star ground

design approach is typically used to keep circuit

block currents isolated (high-power/low-power

small-signal) which reduces noise-coupling and

ground-bounce issues. A single ground plane

for this design gives good results. With this

small layout and a single ground plane, there is

ground-bounce

issue,

and

having

the

components segregated minimizes coupling

between signals.

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