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Data Sheet #: TM084
Page 4 of 44
Rev: P02
Date: 12/5/06
© Copyright 200
6 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC4130
Synchronous Clock for SETS
Data Sheet
STC4130 Pin Description
Table 1: Pin Description
Pin Name
Pin #
I/O1
Description
Vdd33
6,22,31,
44,59,
69,80,
89,97
I
3.3V power input
Vdd18
9,18,27,
38,47,53,
65,73,84,
92
I
1.8V power input
Vss
3,13,15,
20,29,35,
41,49,56,
62,67,71,
78,82,87,
95
Digital ground
AVdd18
1, 76
1.8V analog power input
Avss
75, 100
Analog ground
TRST
94
I
JTAG reset
TCK
93
I
JTAG clock
TMS
91
I
JTAG mode selection
TDI
90
I
JTAG data input
TDO
88
O
JTAG data output
RESET
30
I
Active low to reset the chip
MCLK
99
I
Master clock input, 10 MHZ or 20 MHz
MCLK_FRQ_SEL
98
I
Master clock frequency select, 0 = 10 MHz or 1 = 20 MHz
BUS_MODE0
63
I
Bus mode selection, 00: SPI, 01: Motorola, 10: Intel, 11: Multiplex
BUS_MODE1
64
I
Bus mode selection, 00: SPI, 01: Motorola, 10: Intel, 11: Multiplex
BUS_CS
45
I
Parallel bus or SPI Chip select
BUS_ALE
46
I
Parallel bus address latch or SPI clock input
BUS_WRB
48
I
Parallel bus write or SPI data input
BUS_RDB
50
I
Parallel bus read or read/write input
BUS_RDY
51
O
Parallel bus ready output or SPI data output
BUS_A6
61
I
Bus Address bit 6
BUS_A5
60
I
Bus Address bit 5
BUS_A4
58
I
Bus Address bit 4
BUS_A3
57
I
Bus Address bit 3
BUS_A2
55
I
Bus Address bit 2
BUS_A1
54
I
Bus Address bit 1
BUS_A0
52
I
Bus Address bit 0
BUS_AD7
43
I/O
Parallel bus address/data bit7
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