APM32E103CCT6-R datasheet(26/79 Pages) GEEHY

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block includes system memory area and option byte; the system memory area stores

BootLoader, 96-bit unique device ID and capacity information of main memory area; the system

memory area has been written into the program and cannot be erased.

Table5 On-chip Memory Area

Memory

Maximum

capacity

Function

Main memory

area

512 KB

Store user programs and data.

SRAM

128 KB

CPU can access at 0 waiting cycle (read/write).

System memory

area

2KB

Store BootLoader, 96-bit unique device ID, and main memory area

capacity information

Option byte

16Bytes

Configure main memory area read-write protection and MCU working

mode

4.4.1.

External Memory Controller（EMMC）

EMMC includes SMC (static memory controller) and DMC (dynamic memory controller). SMC is

responsible for controlling SRAM, PSRAM, NandFlash, NorFlash and PCCard; DMC is

responsible for controlling SDRAM.

Function：

⚫

Three EMMC interrupt sources，through logic or connected to the NVIC list

⚫

Write FIFO

⚫

Code could run on external storage besides NAND Flash and PC card

⚫

Connect with LCD

4.4.2.

LCD parallel interface

EMMC can be configured to the seamless connection with most graphic LCD controller, it

supports the Intel 8080 and Motorola 6800 model, and can be flexibly with specific LCD

interface. Using the parallel interface LCD can be easily build simple graphics applications, or

use a special scheme of high performance speed controller.

4.5.

Clock

Clock tree of APM32E103xCxE is shown in the figure below:

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