27C64-150 datasheet(3/12 Pages) STMICROELECTRONICS

3 / 12 page

be used to gate data to the output pins, inde-

pendent of device selection. Assuming that the

addresses are stable, the address access time

(tAVQV) is equal to the delay from E to output (tELQV).

Data is available at the output after a delay of tGLQV

from the falling edge of G, assuming that E has

been low and the addresses have been stable for

at least tAVQV-tGLQV.

Standby Mode

The M27C64A has a standby mode which reduces

the active current from 30mA to 100

µA. The

M27C64A is placed in the standby mode by apply-

ing a CMOS high signal to the E input. When in the

standby mode, the outputs are in a high impedance

state, independent of the G input.

Two Line Output Control

Because EPROMs are usually used in larger mem-

ory arrays, this product features a 2 line control

function which accommodates the use of multiple

memory connection. The two line control function

allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control lines,

E should be decoded and used as the primary

device selecting function, while G should be made

a common connection to all devices in the array

and connected to the READ line from the system

control bus. This ensures that all deselected mem-

ory devices are in their low power standby mode

and that the output pins are only active when data

is required from a particular memory device.

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

devices. The supply current, ICC, has three seg-

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

the transient current peaks is dependent on the

capacitive and inductive loading of the device at the

output.

The associated transient voltage peaks can be

suppressed by complying with the two line output

control and by properly selected decoupling ca-

pacitors. It is recommended that a 0.1

µF ceramic

capacitor be used on every device between VCC

and VSS. This should be a high frequency capacitor

of low inherent inductance and should be placed

as close to the device as possible. In addition, a

4.7

µF bulk electrolytic capacitor should be used

between VCC and VSS for every eight devices. The

bulk capacitor should be located near the power

supply connection point. The purpose of the bulk

capacitor is to overcome the voltage drop caused

by the inductive effects of PCB traces.

Mode

PA9

VPP

Q0 - Q7

Read

VIL

VIH

XVCC

Data Out

Output Disable

VIL

VIH

XVCC

Hi-Z

Program

VIL

VIH

VIL Pulse

VPP

Data In

Verify

VIL

VIH

XVPP

Data Out

Program Inhibit

VIH

VPP

Hi-Z

Standby

VIH

VCC

Hi-Z

Electronic Signature

VIL

VIH

VID

VCC

Codes

Note: X = VIH or VIL, VID = 12V

± 0.5V

Table 3. Operating Modes

Identifier

Hex Data

Manufacturer’s Code

VIL

001

9Bh

Device Code

VIH

000

08h

Table 4. Electronic Signature

3/12

M27C64A

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