PCA9601DPZ datasheet(5/31 Pages) NXP

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NXP Semiconductors

PCA9601

Dual bidirectional bus buffer

maximum of 15 V even without VCC present. The input configuration on SX and RX also

presents no loading of external signals when VCC is not present.

The effective input capacitance of any signal pin, measured by its effect on bus rise

times, is less than 10 pF for all bus voltages and supply voltages including VCC = 0 V.

7.3 Connections to other bus buffers

Two or more SX or SY I/Os must not be interconnected. The PCA9601 design does

not support this configuration. Bidirectional I2C-bus signals do not allow any direction

control pin so, instead, slightly different logic LOW voltage levels are used at SX/SY

to avoid latching of this buffer. A ‘regular I2C-bus LOW’ applied at the RX/RY of a

PCA9601 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage

level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9601, that

second PCA9601 will not recognize it as a ‘regular I2C-bus LOW’ and will not propagate

it to its TX/TY output. The SX/SY side of PCA9601 may not be connected to similar

buffers that rely on special logic thresholds for their operation, for example P82B96,

PCA9511A, PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for,

and compatible with, the normal I2C-bus logic voltage levels of I2C-bus master and slave

chips, or even TX/RX signals of a second PCA9601 or P82B96 if required. The TX/RX

and TY/RY I/O pins use the standard I2C-bus logic voltage levels of all I2C-bus parts.

There are

no restrictions on the interconnection of the TX/RX and TY/RY I/O pins to

other PCA9601s, for example in a star or multipoint configuration with the TX/RX and

TY/RY I/O pins on the common bus and the SX/SY side connected to the line card slave

devices. For more details see Application Note AN10658, "Sending I2C-bus signals via

long communication cables".

7.4 Comparison of PCA9601/PCA9600 and P82B96

The PCA9601 is a direct upgrade of the P82B96 with the significant differences

summarized in Table 4. The PCA9601 provides improved interface to the higher drive

Fast-mode Plus devices on the SX/SY sides.

Detail

PCA9601/PCA9600

P82B96

Supply voltage (VCC) range:

2.5 V to 15 V

2 V to 15 V

Maximum operating bus voltage

(independent of VCC):

15 V

Typical operating supply current:

5 mA

1 mA

Typical LOW-level input voltage on I2C-bus

(SX/SY side):

0.5 V over -40 °C to +85 °C

0.65 V at 25 °C

LOW-level output voltage on I2C-bus (SX/SY

side; 3 mA sink):

0.74 V (max.) over -40 °C to +85 °C

0.88 V (typ.) at 25 °C

LOW-level output voltage on Fm+ I2C-bus

(SX/SY side; 15 mA sink):

1 V (max.) over 0 °C to 85 °C

(PCA9601 only)

n/a

Temperature coefficient of VIL / VOL:

0 mV/°C

-2 mV/°C

Logic voltage levels on SX/SY bus

(independent of VCC):

compatible with I2C-bus and similar

buses using TTL levels (SMBus, etc.)

compatible with I2C-bus and similar

buses using TTL levels (SMBus, etc.)

Typical propagation delays:

< 100 ns

< 200 ns

Table 4. PCA9601/PCA9600 versus P82B96

PCA9601

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 4 January 2022

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