256Kx16 LP SRAM EM6156K600V Series

5

DCC-SR-041003-A

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

Notes :

1.WE# is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low.

3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.

4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.

High-Z

Valid Data

Address

Dout

CE#

OE#

LB#, UB#

Address

Dout

Previous Data Valid

Data Valid