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M494B1 bảng dữ liệu(PDF) 7 Page - STMicroelectronics |
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M494B1 bảng dữ liệu(HTML) 7 Page - STMicroelectronics |
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7 / 22 page ![]() D0 D1 D2 D3 D4 DISPLAY DRIVE 640 µs ( 2ms) MUX PERIOD (8ms) Figure 5 FUNCTIONAL DESCRIPTION (continued) Display, Keyboard and Data Multiplexing Logic is integrated on the chip to provide the mul- tiplexing between the display, keyboard and data inputs. In the On state and with the Data Hand- shake pin at logic HI as an input the display and keyboard are muxed together. See Figure 5. Each column output goes to logic LO in sequence and the row inputs are scanned for a key closure. In chronological order across the total mux. period there is : initialisation, scan, decision and display periods. The Data Handshake pin has a complex logical function. It has two modes of operation : as a hand shake I/O line to a µP and as an output line to the P to signal that the M494 is in the Off state. In order to achieve this function careful signal timing is required both internally and externally to the chip. See Figure 6. When the device is in the OFF state the Data Handshake pin is used to signal this condition to the µP by being pulled LO. A1 B1 C1 D1 A2 B2 C2 D2 A3 DATA DATA O/I I/O O/I I/O (EOT = END OF TRANSMISSION) K/B AND RC I/P DISABLED TILL EOT EXECYTION DATA HANDSHAKE D0 - D4 EOE (END OF TRANSMISSION) NOT TO SCALE DATA HANDSHAKE PIN CONFIGURATION t RTS t CTS t O/P t H t CR t S t j t HS t CR t O/P t CTS Figure 6 : Data-input-timing N ° Symbol Parameter Min. Typ. Max. Unit 1tRTS Request to Send Pulse (RTS) 5 10 µs 2tCTS Clear to Send (CTS) 512 µs 3tO/P Pin Output Configuration 8 ms 4tHS Handshake Time 12 µs 5tS Data Set up Time 10 128 µs 6tH Data Hold Time 128 256 µs 7tJ Synchronization Jitter 8 ms 8tCR CTS to next RTS Pulse 98 ms Note : Oscillator Clock = 500kHz M494 7/22 |
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