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BLOCK DIAGRAM

+

−

input buffer

stage

VML output

buffer

Q

Q

input buffer

stage

+

-

VML output

buffer

Q

Q

MUX

I1

I2

Q

SEL

reference voltage and

bias current generation

VDD

GND

VDD

GND

RXB+

RXB−

TXA+

TXA−

RXA+

RXA−

TXB+

TXB−

RCLK

low−noise

half−rate clock

synthesizer PLL

ICLK

RCLK

QCLK

signal

conditioning PLL

ICLK

DOUT

DIN

QCLK

signal

conditioning PLL

ICLK

DIN

DOUT

QCLK

2

2

2

amplifier

stage

2

MUX

I1

I2

Q

SEL

2

LBB

ENB

ENA

LBA

2

2

2

2

DATA PATHS

TLK1002A

DUAL SIGNAL CONDITIONING TRANSCEIVER

SLLS661 – JUNE 2005

A simplified block diagram of the TLK1002A circuit is shown in Figure 1. The main circuit parts are described in

detail below.

Figure 1. Simplified Block Diagram of the TLK1002A Transceiver

The serial input data streams are connected to the input ports RXA+/RXA– or RXB+/RXB– respectively. The

input stages provide on-chip differential 100-

Ω termination. The outputs of the input buffer stages are connected

to the signal conditioning PLL circuits.

The PLL output signals are fed to multiplexer (MUX) stages, which are used to redirect the data signals if loop

back mode is selected.

The multiplexer stages are connected to the output ports TXB+/TXB– or TXA+/TXA– , respectively, by means of

VML output buffer stages. To enable the output buffer stages, ENA and ENB, which are internally pulled up,

must be at high level (VDD).

The loop back modes are enabled by means of the control-inputs LBA and LBB, which are implemented as

active low inputs with integrated pull-up resistors. If LBA is set to low level, the input data applied to the input port

RXA+/RXA– is retimed and fed to both output ports TXB+/TXB– and TXA+/TXA–. If LBB is pulled low, the

retimed input data signal applied to RXB+/RXB– is available at TXA+/TXA– and TXB+/TXB–.

If a logic low signal is applied to both loop back control inputs the retimed signal connected to RXA+/RXA–

appears at TXA+/TXA–, while the retimed signal applied to RXB+/RXB– is fed to TXB+/TXB–.

2