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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SMC032AF bảng dữ liệu(PDF) 42 Page - Numonyx B.V |
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SMC032AF bảng dữ liệu(HTML) 42 Page - Numonyx B.V |
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42 / 82 page  Software interface SMCxxxAF 42/82 7.4 I/O primary and secondary address configurations (conf = 2,3) When the system decodes the primary and secondary address configurations, the registers are accessed in the block of I/O space as shown in Table 38. As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2 Low (and A0 Don’t care) as a word register on the combined odd and even data bus (D15 to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte accesses to offset 0. The address space of this word register overlaps the address space of the error and feature bytewide registers at offset 1. When accessed twice as byte register with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register. Table 38. Primary and secondary I/O decoding – REG A9 to A4 A3 A2 A1 A0 – IORD=0 – IOWR=0 0 1F(17)h 0 0 0 0 Even Data register Even Data register 0 1F(17)h 0 0 0 1 Error register Feature register 0 1F(17)h 0 0 1 0 Sector Count register Sector Count register 0 1F(17)h 0 0 1 1 Sector Number register Sector Number register 0 1F(17)h 0 1 0 0 Cylinder Low register Cylinder Low register 0 1F(17)h 0 1 0 1 Cylinder High register Cylinder High register 0 1F(17)h 0 1 1 0 Select Card/Head register Select Card/Head register 0 1F(17)h 0 1 1 1 Status register Command register 0 3F(37)h 0 1 1 0 Alternate Status register Device Control register 0 3F(37)h 0 1 1 1 Drive Address register Reserved |
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