MPC8245 datasheet(59/68 Pages) FREESCALE

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MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Document Revision History

0.4

—

Section 1.2—Changed Features list (format) to match with the features list of the MPC8245 Integrated

Processor Reference Manual.

Section 1.4.1.2—Updated Table 2 to include 1.8 ± 100mV numbers.

Section 1.4.3—Changed Table 7 to include new part offerings of 333 and 350 MHz. Added rows to

include VCO frequency ranges for all parts for both memory VCO and CPU VCO.

Section 1.4.1.5—Updated power consumption table to include 1.8 V (VDD) and higher frequency

numbers.

Section 1.4.3—Updated Table 7 to include higher frequency offerings and CPU VCO frequency range.

Section 1.4.3.1—Changed lettering to caps for DLL_EXTEND and DLL_MAX_DELAY in graph

description section.

Section 1.4.3.2—Changed name of item 11 from Tsu—SDRAM_SYNC_IN to PCI_SYNC_IN Time to

Tos—SDRAM_SYNC_IN to sys_logic_clk Offset Time. Changed name to Tos in Note 7 as well.

Section 1.6—Updated notes in Table 17. Included minimum and maximum VCO numbers for memory

VCO. Changed Note 13 for location of PLL_CFG[0:4] to correct bits location. Bits 7–4 of register offset

<0xE2>. Added Table 18 to cover PLL configuration of higher frequency part offerings.

Section: 1.7—Changed frequency ranges for reference numbers 0, 9, 10, and 17, for the 300-MHz part

to include the higher memory bus frequencies when operating at lower CPU bus frequencies. Added

Table 18 to include PLL configurations for the 333 MHz and the 350 MHz CPU part offerings. Added

VCO multipliers in Tables 17 and 18.

Section 1.7.8—Changed Tsu—SDRAM_SYNC_IN to PCI_SYNC_IN Time to Tos—SDRAM_

SYNC_IN to sys_logic_clk Offset Time.”

Section 1.7.10—Added vendor (Cool Innovations, Inc.) to list of heat sink vendors.

0.3

—

Section 1.4.1.5—Changed Max-FP value for 33/133/266 of Table 5 from 2.3 to 2.1 watts to represent

characterization data. Changed Note 4 to say VDD = 2.1 for power measurements (for 2-V part).

Changed numbers for maximum I/O power supplies for OVDD and GVDD to represent characterization

data.

Section 1.4.3.1—Added four graphs (Figures 5–8) and description for DLL Locking Range vs.

Frequency of Operation to replace Figure 5 of Rev 0.2 document.

Section 1.4.3.2—Added row (item 11: Tsu—SDRAM_SYNC_IN to PCI_SYNC_IN timing) to Table 9 to

include offset change requirement.

Section 1.5.3—Changed Note 4 of PLL_CFG pins in Table 16 to Note 20.

Section 1.7.2—Added diode (MUR420) to Figure 27, Voltage Sequencing Circuit, to compensate for

voltage extremes in design.

Section 1.7.5—Added sentence with regards to SDRAM_SYNC_IN to PCI_SYNC_IN timing

requirement (Tsu) as a connection recommendation.

Section 1.7.8—Mention of Tsu offset timing and driver capability differences between the MPC8240

and the MPC8245.

Table 19. Revision History Table (continued)

Revision

Date

Substantive Change(s)

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