M95256 datasheet(16/43 Pages) STMICROELECTRONICS

16 / 43 page

Instructions

M95256, M95256-W, M95256-R

16/43

5.3

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Write or Write Status Register cycle

is in progress. When one of these cycles is in progress, it is recommended to check the

Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the Status Register continuously, as shown in Figure 7.

The status and control bits of the Status Register are as follows:

5.3.1

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such

cycle is in progress.

5.3.2

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write or Write Status Register instruction is accepted.

5.3.3

BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Write instructions. These bits are written with the Write Status

1, the relevant memory area (as defined in Table 4) becomes protected against Write

(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

5.3.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware Protected mode (when the Status Register

Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the

non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the

Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 4.

Status Register format

SRWD

BP1

BP0

WEL

WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

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