AT25FF321A datasheet(64/112 Pages) RENESAS

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DS-AT25FF321A-181 Rev. R

Page 64

2024-12-20

AT25FF321A Datasheet

6.11 Program/Erase Suspend (75h/B0h)

The device supports two Program/Erase Suspend commands, 75h and B0h, that perform the exact same

function. The 75h command can be used for legacy software, and the B0h command is used for compatibility with

future implementations.

In some code plus data storage applications, it is often necessary to process certain high-level system interrupts

that require relatively immediate reading of code or data from the Flash memory. In such an instance, it may not

be possible for the system to wait the microseconds or milliseconds required for the Flash memory to complete a

program or erase cycle. The Program/Erase Suspend command allows a program or erase operation in progress

to be suspended so that other device operations can be performed. For example, by suspending an erase

operation to a particular block, the system can perform functions such as a program or read to a different block.

6.11.1

Transfer Format

The 75h and B0h commands follow the 1-0-0 transfer format described in Section 4.2, where the command is

transferred on the SI pin. No address or data are transferred for this command. See Figure 3 for a timing diagram

of this operation.

6.11.2

Transfer Sequence

To perform the Program Erase/Suspend operation, the CS pin is asserted and the information transferred as

follows:

▪ The 75h or B0h command is clocked into the device. Eight clocks are required to transfer the command. The

most significant bit of the command is transferred first.

▪ When the CS pin is deasserted, the device suspends the program.

See Table 18 for more information on the transfer sequence for this command.

6.11.3

Command Behavior During a Program/Erase Operation

If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a

Write Status Register operation, then the device simply ignores the command and no operation is performed. The

state of the WEL bit in Status Register 1 is not affected. Note that in the table below, the RDY/BSY bit is located in

Status Register 1. The PS and ES bits are located in Status Register 5.

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