ST7FLCD1_05 datasheet(73/95 Pages) STMICROELECTRONICS

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ST7FLCD1

Display Data Channel Interfaces (DDC)

Bits [7:0] = D[7:0] 8-bit Data Register.

These bits contain the byte to be received or transmitted on the bus.

Transmitter mode: Bytes are automatically transmitted when the software writes to the DR

Receiver mode: The first data byte is automatically received in the DR register using the least

significant bit of the address. Then, the next data bytes are received one by one after reading the

DR register.

DDC OWN ADDRESS REGISTER 1 (DDCOAR1)

Read / Write

Reset Value: 0000 0000 (00h)

Bits [7:1] = ADD[7:1] Interface address.

These bits define the I²C bus programmable address of the interface. They are not cleared when

the interface is disabled (PE = 0).

Bit 0 = Reserved. Forced to 0 by hardware.

DDC OWN ADDRESS REGISTER 2 (DDCOAR2)

Read / Write

Reset Value: 0000 0000 (00h)

Bits [7:1] = ADD[7:1] Interface address.

These bits define the I²C bus programmable address of the interface. They are not cleared when

the interface is disabled (PE = 0).

Bit 0 = Reserved. Forced to 0 by hardware.

DDC2B CONTROL REGISTER (DDCDCR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits [7:6] = Reserved. Forced by hardware to 0.

Bit 5 = ENDCF End of Communication interrupt Flag.

This bit is set by hardware. An interrupt is generated if ENDCE = 1. It must be cleared by software.

NACK or STOP condition not met in Read mode.

765

432

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

765

432

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

765

432

ENDCF

ENDCE

EDF

EDE

DDC2BPE

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