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STA33013TR bảng dữ liệu(PDF) 19 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  2.0 digital audio processor with FFX digital modulator and analog and digital inputs
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STA330
PLL
19/55
If register bit PLLCFG0.FRAC_CTRL = 0, then:
FVCO = FINFIN * LDF
FPHI = FVCO / ODF
In the above equations:
FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0]
IDF = Input division factor (refer to previous formulas)
LDF = Loop division factor (refer to previous formulas)
ODF = Output division factor = 2
FINFIN = INFIN frequency
FXTI = XTI frequency
FVCO = VCO frequency
FPHI = Frequency of the PLL output clock
When selecting the value of IDF, LDF and FRACT make sure the following limits are
maintained:
2.048 MHz < FXTI < 49.152 MHz
2.048 MHz < FINFIN < 16.384 MHz
65.536 MHz < FVCO < 98.304 MHz
There are also some additional constraints on IDF and LDF. IDF should be greater than 0,
LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1.
When automatic settings are not used, the PLL must be configured to generate an internal
frequency of N * fS, where fS is the LRCLKI pin frequency. Values of N are given in Table 11.
Table 11.
Oversampling table
fS (kHz)
N
FPHI (MHz)
8
4096
32.768
11.025
4096
45.1584
12
4096
49.152
16
2048
32.768
22.05
2048
45.1584
24
2048
49.152
32
1024
32.768
44.1
1024
45.1584
48
1024
49.152
64
512
32.768
88.2
512
45.1584
96
512
49.152
128
256
32.768
176.4
256
45.1584
192
256
49.152



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