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W134M/W134S
Document #: 38-07426 Rev. *C
Page 6 of 12
Timing Diagrams
Table 8. State Transition Latency Specifications
Transition
From
To
Transition Latency
Description
Parameter
Max.
A
Power-down
Normal
tPOWERUP
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
C
Power-down
Clk Stop
tPOWERUP
3 ms
Time from PwrDnB until the internal PLL and clock has
turned ON and settled.
K
Power-down
Test
tPOWERUP
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
GVDD ON
Normal
tPOWERUP
3 ms
Time from VDD is applied and settled until Clk/ClkB
output settled (excluding tDISTLOCK).
HVDD ON
Clk Stop
tPOWERUP
3 ms
Time from VDD is applied and settled until internal PLL
and clock has turned ON and settled.
MVDD ON
Test
tPOWERUP
3 ms
Time from VDD is applied and settled until internal PLL
and clock has turned ON and settled.
J
Normal
Normal
tMULT
1 ms
Time from when Mult0 or Mult1 changed until Clk/ClkB
output resettled (excluding tDISTLOCK).
tPOWERUP
tPOWERDN
tSTOP
tON
tCLKON
tCLKOFF
tCLKSETL
PwrDnB
Clk/ClkB
Power-down Exit and Entry
Output Enable Control
StopB
Clk/ClkB
Output clock
not specified
glitches may
Clock enabled
and glitch-free
Clock output settled within
50 ps of the phase before
disabled
occur
Figure 5. State Transition Timing Diagrams
tMULT
Clk/ClkB
Mult0 and/or Mult1
Figure 6. Multiply Transition Timing
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