CYWUSB6932
CYWUSB6934
Document 38-16007 Rev. *I
Page 13 of 30
Addr: 0x09
REG_RX_DATA_A
Default: 0x00
7
654
3210
Data
Figure 7-8. Receive SERDES Data A
Bit
Name
Description
7:0
Data
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Addr: 0x0A
REG_RX_VALID_A
Default: 0x00
7
654
3210
Valid
Figure 7-9. Receive SERDES Valid A
Bit
Name
Description
7:0 Valid
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the
corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A register
(Reg 0x0A) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0C). This register is
read-only.
Addr: 0x0B
REG_RX_DATA_B
Default: 0x00
7
654
3210
Data
Figure 7-10. Receive SERDES Data B
Bit
Name
Description
7:0
Data
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Figure 7-11. Receive SERDES Valid B
Addr: 0x0C
REG_RX_VALID_B
Default: 0x00
7
654
3210
Valid
Bit
Name Description
7:0
Valid
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the
corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register
(Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C). This register is
read-only.
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
