AD9960

Rev. 0 | Page 5 of 12

Table 3. Auxiliary ADC and DAC Specifications

Parameter

Min

Typ

Max

Unit

AUXILIARY ADC

Resolution

10

Bits

ADC Monotonicity

Guaranteed

Input Range1

0

AVDD

V

Conversion Rate

μs

AUXILIARY DAC

Resolution

10

Bits

DAC Monotonicity

Guaranteed

Input Range1

0

AVDD

Slew Rate (Normal)

0.45

V/μs

Slew Rate (Boost)

1.7

V/μs

Settling Time (Normal)

300

kHz

Settling Time (Boost)

960

kHz

1 AUXADC and AUXDAC full-scale span can be set to AVDD supply or programmable regulator voltage (2.52 V, 2.7 V, 3.0 V).

Table 4. Power Specifications

Parameter

Min

Typ

Max

Unit

POWER SUPPLY RANGE

ADC Supply Voltage (ADCVDD)

3.0

3.3

3.6

V

DAC Supply Voltage (DACVDD)

3.0

3.3

3.6

V

Auxiliary Supply Voltage (AUXVDD)

3.0

3.3

3.6

V

Clock Supply Voltage (CLKVDD)

3.0

3.3

3.6

V

Digital Supply Voltage (DVDD)

2.7

3.3

3.6

V

Driver Supply Voltage (DRVDD)

2.7

3.3

3.6

V

ANALOG SUPPLY CURRENTS

ADCVDD (Nominal Bias)

104

114

mA

DACVDD (20 mA Full-Scale Outputs)

68

73

mA

AUXVDD

2

3

mA

CLKVDD

2

3.5

mA

DIGITAL SUPPLY CURRENTS1

DVDD (Tx Mode)

116

140

mA

DVDD (Rx Mode)

107

135

mA

DRVDD (Tx Mode)

5

mA

DRVDD (Rx Mode) with CLOAD = 5 pF2

5

mA

1 Rx digital and analog path configured for bypass mode.

2 DRVDD in Rx mode is dependent on ADIO bus load capacitance.