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CY29653
Document #: 38-07477 Rev. *C
Page 4 of 7
Note:
7. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies
within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
VCMR
Common Mode Range[7]
LVPECL
1.2
–
VDD – 0.9
V
fMAX
Maximum Output Frequency
÷4 Output
35
–
125
MHz
÷8 Output
25
–
62.5
DC
Output Duty Cycle
45
–
55
%
tr, tf
Output Rise/Fall times
0.55V to 2.4V
0.1
–
1.0
ns
t(φ)
Propagation Delay (static phase
offset)
PCLK to FB_IN
–200
–
200
ps
tPD
Propagation Delay (PLL and
divider bypass)
PCLK to Q0 – Q7
BYPASS# = 0
3.6
4.8
6.0
ns
tsk(O)
Output-to-Output Skew
–
30
150
ps
tPLZ, HZ
Output Disable Time
–
–
6
ns
tPZL, ZH
Output Enable Time
–
–
6
ns
BW
PLL Closed Loop Bandwidth
(–3 dB)
÷4 Feedback
–
1.8 – 2.1
–
MHz
÷8 Feedback
–
1.4 – 1.6
–
tJIT(CC)
Cycle-to-Cycle Jitter
–
30
100
ps
tJIT(PER)
Period Jitter
–
45
100
ps
tJIT(φ)
I/O Phase Jitter
–
–
150
ps
tLOCK
Maximum PLL Lock Time
–
–
1
ms
AC Parameters (VDD = 3.3V ± 5%, TA = operating temperature range) (continued)[3]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
RT = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
Figure 1. AC Test Reference
t(
φ)
PECL_CLK
PECL_CLK
VPP
FB_IN
VCMR
VDD
GND
VDD/2
Figure 2. Propagation Delay t(
φ), Static Phase Offset
tPD
PECL_CLK
PECL_CLK
VPP
Qn
VCMR
VDD
GND
VDD/2
Figure 3. Propagation Delay tPD, PLL Bypass
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