3

5132BS–TPM–1/08

AT97SC3203S

Figure 2-2.

AT97SC3203S Block Diagram

2.

Description (continued)

Communication to and from the TPM occurs through a modified 100-kHz SMBus two-wire inter-

face. The TPM includes a hardware random number generator, including a FIPS-approved

Pseudo Random Number Generator, that is used for key generation and TCG protocol func-

tions. The RNG is also available to the system to generate random numbers that may be needed

during normal operation.

The chip uses a dynamic internal memory management scheme to store multiple RSA keys.

Other than the standard TCG commands (TPM_FlushSpecific, TPM_Loadkey2), no system

intervention is required to manage this internal key cache.

protocol information.

33 MHz

AVR

Clock Input

AVR

8-Bit RISC

CPU

Physical

Security

Circuitry

SMBDAT

SMBus Interface

GPIO

RTC

(Optional)

32.768 kHz

RNG

Timer

ROM

Program

EEPROM

Program

EEPROM

Data

CRYPTO

Engine

SRAM

GPIO6

SMBCLK