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STM32F427AI bảng dữ liệu(PDF) 144 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  32b Arm® Cortex®-M4 MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera & LCD-TFT
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Electrical characteristics
STM32F427xx STM32F429xx
144/240
DS9405 Rev 12
tw(SCKH)
SCK high and low time
Master mode, SPI presc = 2,
2.7 V≤VDD≤3.6 V
TPCLK − 0.5
TPCLK
TPCLK+0.5
ns
tw(SCKL)
Master mode, SPI presc = 2,
1.7 V≤VDD≤3.6 V
TPCLK − 2
TPCLK
TPCLK+2
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4TPCLK
--
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2TPCLK
tsu(MI)
Data input setup time
Master mode
3
-
-
tsu(SI)
Slave mode
0
-
-
th(MI)
Data input hold time
Master mode
0.5
-
-
th(SI)
Slave mode
2
-
-
ta(SO)
Data output access time Slave mode, SPI presc = 2
0
-
4TPCLK
tdis(SO)
Data output disable time
Slave mode, SPI1/4/5/6,
2.7 V≤VDD≤3.6 V
0-
8.5
Slave mode, SPI1/2/3/4/5/6 and
1.7 V≤VDD≤3.6 V
0-
16.5
tv(SO)
th(SO)
Data output valid/hold
time
Slave mode (after enable edge),
SPI1/4/5/6 and 2.7V ≤ VDD ≤ 3.6V
-11
13
ns
Slave mode (after enable edge),
SPI2/3, 2.7 V≤VDD≤3.6 V
-14
15
Slave mode (after enable edge),
SPI1/4/5/6, 1.7 V≤VDD≤3.6 V
-15.5
19
Slave mode (after enable edge),
SPI2/3, 1.7 V≤VDD≤3.6 V
-
15.5
17.5
tv(MO)
Data output valid time
Master mode (after enable edge),
SPI1/4/5/6, 2.7 V≤VDD≤3.6 V
--
2.5
Master mode (after enable edge),
SPI1/2/3/4/5/6, 1.7 V≤VDD≤3.6 V
--
4.5
th(MO)
Data output hold time
Master mode (after enable edge)
0
-
-
1. Evaluated by characterization.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK
low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
Table 63. SPI dynamic characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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