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CY7C09279V-9AI bảng dữ liệu(PDF) 1 Page - Cypress Semiconductor

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Giải thích chi tiết về linh kiện  3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06056 Rev. *B
Revised April 6, 2005
1CY7C025/0251
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 6 Flow-Through/Pipelined devices
— 16K x 16/18 organization (CY7C09269V/369V)
— 32K x 16/18 organization (CY7C09279V/379V)
— 64K x 16/18 organization (CY7C09289V/389V)
• 3 Modes
— Flow-Through
— Pipelined
—Burst
• Pipelined output mode on both ports allows fast
100-MHz operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[1, 2]/7.5[2]/9/12 ns
(max.)
• 3.3V low operating power
— Active = 115 mA (typical)
— Standby = 10
µA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Pb-Free 100-pin TQFP Package Available
Notes:
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
4. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
5. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
Logic Block Diagram
R/WL
1
0
0/1
CE0L
CE1L
LBL
OEL
UBL
1b
0/1
0b 1a 0a
ba
FT/PipeL
I/O8/9L–I/O15/17L
I/O0L–I/O7/8L
I/O
Control
Counter/
Address
Register
Decode
A0L–A13/14/15L
CLKL
ADSL
CNTENL
CNTRSTL
True Dual-Ported
RAM Array
R/WR
1
0
0/1
CE0R
CE1R
LBR
OER
UBR
1b
0/1
0b
1a
0a
b
a
FT/PipeR
I/O
Control
Counter/
Address
Register
Decode
14/15/16
8/9
8/9
I/O8/9R–I/O15/17R
I/O0R–I/O7/8R
A0R–A13/14/15R
CLKR
ADSR
CNTENR
CNTRSTR
14/15/16
8/9
8/9
[3]
[4]
[3]
[4]
[5]
[5]
CY7C09269V CY7C09279V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM


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