CY7C419/21/25/29/33
Document #: 38-06001 Rev. *B
Page 11 of 25
Architecture
The
CY7C419,
CY7C420/1,
CY7C424/5,
CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of
dual-port RAM cells), a read pointer, a write pointer, control
signals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and
Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is
necessary to achieve truly asynchronous operation of the
inputs and outputs. A second benefit is that the time required
to increment the read and write pointers is much less than the
time that would be required for data propagation through the
memory, which would be the case if the memory were imple-
mented using the conventional register array architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH tRPW/tWPW before and tRMR after the rising
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0–D8) tSD before and tHD after the
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW tWHF after the falling edge of W following the FIFO
actually being Half Full. Therefore, the HF is active once the
Expansion Timing Diagrams
Note:
15. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2).
Switching Waveforms (continued)
R
W
XO1(XI2)
D0–D 8
DATA VALID
DATA
DATA
VALID
VALID
tXOL
tXOH
tHD
tSD
tSD
tHD
tXOL
tLZR
tA
tDVR
tXOH
tA
tDVR
tHZR
XO1(XI2)
Q0–Q 8
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
tWR
tRR
DATA VALID
[15]
[15]
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