LM2655 datasheet(13/16 Pages) NSC

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Application Circuits (Continued)

OBTAINING OUTPUT VOLTAGES OF LESS THAN 1.25V

Some applications require output voltages less than 1.25V.

The circuit shown in Figure 5 will allow the LM2655 to do

such a conversion. By referencing the two feedback resis-

tors to V

ADJ (VADJ > 1.24V), VOUT can be adjusted from 0V

to V

ADJ by the equation:

OUT =(VREF-VADJ)*(RFB1+RFB2)/RFB2 +VADJ

where V

REF = 1.24V. VADJ can be any voltage higher than

REF (1.24V). In Figure 5,VADJ is produced by an LMV431

adjustable reference following the equation:

ADJ = 1.24*(RADJ1/RADJ2 + 1).

Pcb Layout Considerations

Layout is critical to reduce noise and ensure specified per-

formance. The important guidelines are listed as follows:

Minimize the parasitic inductance in the loop of input

capacitors and the internal MOSFETs by connecting the

input capacitors to V

IN and PGND pins with short and

wide traces. The high frequency ceramic bypass capaci-

tor, in particular, should be placed as close to and no

more than 5mm from the V

IN pin. This is important

because the rapidly switching current, together with wir-

ing inductance can generate large voltage spikes that

may result in noise problems.

Minimize the trace from the center of the output resistor

divider to the FB pin and keep it away from noise

sources to avoid noise pick up. For applications that

require tight regulation at the output, a dedicated sense

trace (separated from the power trace) is recommended

to connect the top of the resistor divider to the output.

If the Schottky diode D is used, minimize the traces

connecting D to SW and PGND pins. Use short and wide

traces.

If the low-side MOSFET is used, minimize the trace

connecting the LDR pin to the gate of the MOSFET, and

the traces to SW and PGND pins. Use short and wide

traces for the power traces going from the MOSFET to

SW and PGND pins.

10128424

FIGURE 5. Obtaining output voltages of less than 1.25V

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