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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LAN8808D bảng dữ liệu(PDF) 42 Page - Microchip Technology |
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LAN8808D bảng dữ liệu(HTML) 42 Page - Microchip Technology |
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42 / 80 page  LAN8808D DS00005833C-page 42 © 2026 Microchip Technology Inc. and its subsidiaries 5.12.3 EXTERNAL CONNECTOR LOOPBACK The external connector loopback testing feature allows the twisted pair interface to be looped back externally. This loop- back tests the PHY digital and MAC connectivity. When using this feature, the PHY must be connected to a loopback connector or a loopback cable. Pair A must be connected to pair B, and pair C to pair D, as shown in Figure 5-5. The connector loopback feature functions at all available interface speeds. 5.12.4 QSGMII LOOPBACK This QSGMII loopback testing feature calls various portions of the QSGMII block to be tested, as shown in Figure 5-5. When frames are looped in the QSGMII PCS1G, individual ports are looped, not the entire QSGMII. When frames are looped in the QSGMII SerDes, all four ports are looped. FIGURE 5-5: EXTERNAL CONNECTOR LOOPBACK FIGURE 5-6: QSGMII LOOPBACK PCS PMA LAN8808D MAC Switch or SoC GPHY Port X PCS1G Port X PCS1G PCS1G PCS1G Other Ports MAC MAC MAC Port X QSGMII A B C D QSGMII PCS1G TBI Loopback PCS PMA LAN8808D MAC Switch or SoC Link Partner GPHY Port X PCS1G Port X Other Ports MAC MAC MAC Port X QSGMII PCS1G PCS1G PCS1G PCS PMA LAN8808D MAC Switch or SoC Link Partner GPHY Port X PCS1G Port X Other Ports MAC MAC MAC Port X QSGMII PCS1G PCS1G PCS1G QSGMII PCS1G GMII Loopback LAN8808D MAC Switch or SoC MAC MAC MAC QSGMII QSGMII SerDes Loopback PCS PMA Link Partner GPHY PCS1G Port 3 PCS PMA Link Partner GPHY PCS1G Port 2 PCS PMA Link Partner GPHY PCS1G Port 1 PCS PMA Link Partner GPHY PCS1G Port 0 |
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