Data Sheet

ADRF5420

THEORY OF OPERATION

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Rev. 0 | 10 of 14

The ADRF5420 integrates a driver to perform logic functions inter-

nally and provides the user with the advantage of a simplified

CMOS-compatible and LVTTL-compatible control interface. This

driver features a single digital control input pin, CTRL. The logic

level applied to the CTRL pin determines which RF port is in the

insertion loss state and in the isolation state (see Table 7).

RF INPUT AND OUTPUT

The RF ports (RFC, RF1, and RF2) are DC-coupled to 0 V, and no

DC-blocking is required at the RF ports when the RF line potential

is equal to 0 V. The RF ports are internally matched to 50 Ω.

The ADRF5420 is bidirectional with equal power-handling capabili-

ties. The RF input signal can be applied to the RFC port or the

selected RF throw port.

The insertion loss path conducts the RF signal between the select-

ed RF throw port and the RF common port. The isolation paths

provide high loss between the insertion loss path and the unselect-

ed RF throw port. The unselected RF port of the ADRF5420 is

reflective.

The power handling of the ADRF5420 derates with frequencies less

than 3 GHz and more than 70GHz. See Figure 2 and Figure 3 for

derating of the RF power towards lower and higher frequencies.

POWER SUPPLY

The ADRF5420 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to filter

high frequency noise.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3. Apply the digital control input. Powering the digital control input

before the VDD supply can inadvertently forward bias and

damage the internal ESD protection structures. To avoid this

damage, use a series 1kΩ resistor to limit the current flowing

into the CTRL pin. Use pull-up or pull-down resistors if the

controller is in a high impedance state after VDD is powered up

and the CTRL pin is not driven to a valid logic state.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

Table 7. Control Voltage Truth Table

Digital Control Input (VCTRL)

RF Path

RF1 to RFC

RF2 to RFC

Low

Isolation (off)

Insertion loss (on)

High

Insertion loss (on)

Isolation (off)