MPF0900AMMA2ES datasheet(203/205 Pages) NXP

203 / 205 page

NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

Figures

Fig. 1.

Simplified application diagram i.MX95 ...............4

Fig. 2.

Simplified application diagram i.MX93 ...............5

Fig. 3.

Functional block diagram .................................. 9

Fig. 4.

Internal Block Diagram ....................................10

Fig. 5.

PF09 package pinout (top view) ......................11

Fig. 6.

PF09 Functional state machine .......................18

Fig. 7.

PF09 Startup from cold boot (VAON as

system regulator) ............................................ 30

Fig. 8.

PMIC Startup from Cold boot (VAON

Always-on) .......................................................31

Fig. 9.

PMIC Startup from Cold boot (No default

PWRON event) ............................................... 32

Fig. 10.

PMIC wake-up from DFS ................................ 33

Fig. 11.

Power up/down Transitions ............................. 37

Fig. 12.

Reset counter strategy. ................................... 43

Fig. 13.

Power-down delay ...........................................45

Fig. 14.

RUN and STANDBY transitions ...................... 46

Fig. 15.

Successful power-up (no fault condition) .........56

Fig. 16.

Power-up sequence with temporary failure ..... 56

Fig. 17.

Power-up failure with persistent fault

condition .......................................................... 57

Fig. 18.

Dynamic power-up failure ............................... 58

Fig. 19.

Successful dynamic power-up .........................58

Fig. 20.

PF09 System interface IO signals ...................63

Fig. 21.

XFAILB during Power-up .................................82

Fig. 22.

Bidirectional XFAILB (power-down) .................83

Fig. 23.

Dual PMIC interaction with fault on

controller device .............................................. 83

Fig. 24.

I2C CRC Polynomial ....................................... 85

Fig. 25.

RDSON vs. VLDOUT for LDO1 .................... 113

Fig. 26.

System connection in LDO bypass mode ......116

Fig. 27.

LDOx Bypass mode RUN to STANDBY

transition without voltage scaling ...................118

Fig. 28.

LDOx Bypass mode RUN to STANDBY

transition with voltage scaling ....................... 119

Fig. 29.

RDSON vs. VLDOUT for LDO2/LDO3 .......... 121

Fig. 30.

SW regulator VMON architecture ..................122

Fig. 31.

LDO VMON architecture ............................... 122

Fig. 32.

VAON voltage monitoring architecture .......... 126

Fig. 33.

External VMON resistor divider calculation ... 130

Fig. 34.

External VLDOxMON resistor divider

calculation ......................................................133

Fig. 35.

Triangular modulation ....................................137

Fig. 36.

Pseudo-random modulation .......................... 138

Fig. 37.

Thermal monitoring architecture ....................143

Fig. 38.

PF09 safety architecture diagram ................. 145

Fig. 39.

Dynamic watchdog polynomial ......................149

Fig. 40.

System watchdog operation ..........................151

Fig. 41.

WD_OK counter ............................................ 152

Fig. 42.

ERRMON operation ...................................... 155

Fig. 43.

FCCU bistable protocol ................................. 159

Fig. 44.

FCCU Hybrid bistable operation ....................160

Fig. 45.

FCCU single-ended PWM operation ............. 161

Fig. 46.

Digital machine supervisor block diagram ..... 168

Fig. 47.

Functional bits reset diagram ........................ 180

Fig. 48.

SOT684-32_DD top and bottom views ..........190

Fig. 49.

Detail F ..........................................................191

Fig. 50.

PCB design guidelines - solder mask

opening pattern ............................................. 192

Fig. 51.

PCB design guidelines - I/O pads and

solderable area ............................................. 193

Fig. 52.

PCB design guidelines - solder paste

stencil ............................................................ 194

Fig. 53.

Package outline drawing notes ..................... 195

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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