HV232

DS20005820B-page 8

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TRUTH FUNCTION TABLE

Data in 8-Bit Shift Register

LE

CLR

Output Switch State

D0

D1

D2

D3

D4

D5

D6

D7

SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7

LL

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

X

X

X

X

X

X

X

X

H

L

Hold Previous State

XXX

XXX

XXX

H

All Switches Off

Note 1: The eight switches operate independently.

2: Serial data is clocked in on the L to H transition clock.

3: The switches go to a state retaining their present condition at the rising edge of LE.

4: When LE is low, the Shift register data flow through the latch.

5: DOUT is high when data in the Shift register 7 is high.

6: Shift register clocking has no effect on the switch states if LE is high.

7: The CLR clear input overrides all other inputs.