MPL460A-ISLASH4LB datasheet(16/48 Pages) MICROCHIP

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PL460

Input/Output Lines

Data Sheet

DS60001666D - 16

Input/Output Lines

The PL460 has several kinds of input/output (I/O) lines to manage the device and different features

related to the firmware running in the PL460.

6.1.

Reset (NRST) Pin

The NRST pin is unidirectional. It is managed by the external host controller and can be driven low

to provide a Reset signal to reset the PL460. It resets the core and the peripherals. There is no

constraint on the length of the Reset pulse.

It is recommended to connect the NRST pin to a GPIO of the host controller whose reset state is

configured as pull-down. If the GPIO reset configuration is high-impedance, a pull-down resistor

connected to GND must be used to ensure the timing of the power-on sequence. If using a GPIO

with pull-up as reset configuration, then a 100 nF capacitor connected to GND must be used to

ensure the timing of the power-on sequence.

When using the Sleep mode functionality, the NRST and STBY signals must be connected to a GPIO

in the host controller with an internal pull-down default reset configuration to avoid enabling Sleep

mode until the host boots.

To enter Sleep mode, it is required to reset the device (driving the NRST pin low) before enabling the

STBY input. To exit Sleep mode, the STBY pin must be disabled before releasing NRST.

Refer to Power On Considerations to view the timing constraints using this pin.

6.2.

Enable (ENABLE) Pin

The ENABLE pin is an input and must be driven high to activate the core voltage regulator integrated

within the PL460.

By default, a pull-up resistor to VDDIN is required on this pin. If external management of the

embedded voltage regulator is necessary, the host controller may be used.

For additional information regarding timing constraints associated with this pin, refer to the Power

On Considerations section.

6.3.

Standby (STBY) Pin

The STBY pin is an input. It must be driven high to enable Sleep mode, while keeping the Reset

(NRST) pin enabled (driven low).

By default, the STBY pin must be connected to GND to prevent device malfunction caused by

an undefined status of the PLC line driver pins. If Sleep mode is required, the STBY pin may be

managed accordingly.

In Sleep mode, the core of the device and the peripherals are reset, reducing power consumption.

The content of the RAM memory is maintained. Therefore, the program reloading is not required

when the PL460 returns to normal operating mode.

To avoid device malfunction in Sleep mode due to an undefined status of the PLC line driver pins,

the STBY pin only must be enabled (driven high) after the NRST is enabled (driven low). To exit Sleep

mode, it is required to disable the STBY pin (driven low) first and then, disable NRST (driven high).

When using the Sleep mode functionality, the NRST and STBY signals must be connected to a GPIO

in the host controller with an internal pull-down default reset configuration to avoid enabling Sleep

mode until the host boots.

6.4.

External Interrupt (EXTIN) Pin

The EXTIN signal automatically indicates to the external host controller that the firmware running in

the PL460 has one or more pending events to be consulted by the host controller.

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