7-439

CD4073BMS, CD4081BMS, CD4082BMS

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4073BMS (1 OF 3 IDENTICAL GATES)

FIGURE 2. LOGIC DIAGRAM FOR CD4073BMS (1 OF 3 IDENTICAL GATES)

FIGURE 3. SCHEMATIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)

FIGURE 4. LOGIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)

n

p

*

2 (3, 13)

n

n

*

1 (4, 12)

*

8 (5, 11)

p

n

p

n

p

n

p

9 (6, 10)

p

n

VSS

VDD

p

p

n

ALL INPUTS PROTECTED BY

CMOS PROTECTION NETWORK

VDD

VSS

J

9 (6, 10)

2 (3, 13)

1 (4, 12)

A

B

8 (5, 11)

C

n

p

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

*

2 (5, 9, 12)

p

n

3 (4, 10, 11)

VDD

VSS

n

p

n

n

p

n

p

VDD

VSS

*

1 (6, 8, 13)

p

J

3 (4, 10, 11)

2 (5, 9, 12)

1 (6, 8, 13)

A

B