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LTC1067-50CS bảng dữ liệu(PDF) 7 Page - Analog Devices

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LTC1067/LTC1067-50
PIN FUNCTIONS
V+, V – (Pins 1, 3,14): The V + (Pins 1, 3) and the V – (Pin
14) should each be bypassed with a 0.1
µF capacitor to an
adequate analog ground. The filter’s power supplies should
be isolated from other digital or high voltage analog
supplies. A low noise linear supply is recommended.
Using a switching power supply will lower the signal-to-
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067/LTC1067-50 Mode 1B
Noise Increase vs R5/R6 Ratio
LTC1067/LTC1067-50 Mode 3
Noise Increase vs R2/R4 Ratio
R2/R4 RATIO
0.2
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.5
0.7
1067 G26
0.3
0.4
0.6
0.8
0.9
1.0
noise ratio of the filter. The supply’s power-up slew rate
should be less than 1V/
µs.WhenV+isappliedbeforeV–, and
V – is allowed to go above ground, a diode should clamp V –
to prevent latch-up. Figures 1 and 2 show typical connec-
tions for dual and single supply operation.
0.1
µF
1067 F01
200
Ω
LTC1067
LTC1067-50
CLOCK
SOURCE
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
STAR
SYSTEM
GROUND
DIGITAL
GROUND
PLANE
V+
NC
V+
SA
LPA
BPA
HPA/NA
INV A
CLK
AGND
V–
SB
LPB
BPB
HPB/NB
INV B
V+
V –
0.1
µF
Figure 1. Dual Supply Ground Plane Connections
Figure 2. Single Supply Ground Plane Connections
0.1
µF
106 7 F02
200
Ω
LTC1067
LTC1067-50
CLOCK
SOURCE
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
STAR
SYSTEM
GROUND
DIGITAL
GROUND
PLANE
V+
NC
V+
SA
LPA
BPA
HPA/NA
INV A
CLK
AGND
V–
SB
LPB
BPB
HPB/NB
INV B
V+
1
µF
FOR MODE 3, THE SA AND SB SUMMING NODE PINS
ARE TIED TO THE AGND PIN
R5/R6 RATIO
0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.5
2.5
1067 G25
0.5
1.0
2.0
3.0
3.5



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