L6260 datasheet(14/30 Pages) STMICROELECTRONICS

14 / 30 page

CIRCUIT OPERATION

General

This device includes a sensorless spin driver,

VCM driver, power sequencing, actuator retrac-

tion with dynamic braking, serial interface for a

microprocessor and frequency locked loop for

speed control. The device is register based and

designed to operate via either 3V or 5V power

supply.

POR & Under Voltage

The L6260 has an on chip power monitoring sys-

tem that controls all aspects of powering up,

Power On Reset of the Logic (POR), low voltage

detection and power down sequencing. The cir-

cuitry consists of a Bandgap reference generator,

hysteresis comparitor (for low voltage detection)

and a POR timer circuit (which controls the dura-

tion of the reset).

Four external pins determine the behavior of this

circuit.

UV1 & UV2: These two pins are provided to

the user to connect to the supply voltages for

low voltage detection. The voltage on these

pins is compared to the internal Bandgap volt-

age to determine if a low voltage on one of the

supply pins has been detected. The comparitor

has built in hysteresis to reduce the effects of

noise on the supply lines triggering a false

POR. In other words, if either one of these in-

puts falls below 1.25V then the supply is re-

garded as being ”under voltage”. Normally one

of these pins will be connected to allow a sens-

ing of a 3V supply and the other to the 5V sup-

ply but this is arbitrary

POR_DLY: This is a pin from which a capacitor

can be connected to ground. This sets the du-

ration of the reset state of the this chip. On

power up, an internal current source charges

the capacitor with a current of approximately

2mA. When the voltage on this pin reaches the

bandgap voltage, the chip comes out of its re-

set state. The duration of this reset is deter-

mined by the size of an external capacitor to

ground.

POR: The POR pin is an output from the chip

for resetting other devices.

Frequency Locked Loop Fine Error Counter

(Reg 7)

This register contains the error detected between

the ”fine” counter value of the FLL and the actual

spindle rotation time (in either mechanical or elec-

trical mode).

Reg: 7

Name: FLL Fine Error Counter Register

Type: Read Only

BIT

LABEL

DESCRIPTION

@POR

FINEC BIT 0

FLL Fine error count LSB

FINEC BIT 1

FINEC BIT 2

FINEC BIT 3

FINEC BIT 4

FINEC BIT 5

FINEC BIT 6

FINEC BIT 7

FINEC BIT 8

FINEC BIT 9

FINEC BIT 10

FINEC BIT 11

FLL Fine error count MSB

L6260

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