L6245 datasheet(11/15 Pages) STMICROELECTRONICS

11 / 15 page

Table 1: Status Register (A.C. 001)

Bit

Name

POR Initial

Value

REVERSE SPIN

OVER TEMP.

SPIN SENSE

OVER VEL SET

Table 2: VCM Driver Register (A.C. 010)

Bit

Name

POR Initial

Value

UNLOAD HD

LOAD HD

ENABLE ISENSE

HIGH GAIN VCM

ENABLE VCM

Table 3: Spin Control Register (A.C. 011)

Bit

Name

POR Initial

Value

LINEAR/PWM

INCREMENT STATE

RESET STATE

RUN/SEARCH

UNI/BI

HIGH GAIN SPIN

ENABLE Spin

Table 4: VCM D/A Register (A.C. 100)

Bit

Name

POR Initial

Value

Most Significant Bit

Least Significant Bit

Table 5: Spin D/A Register (A.C. 101)

Bit

Name

POR Initial

Value

Most Significant Bit

Least Significant Bit

Table 6: Interrupt Mask Register (A.C. 110)

Bit

Name

POR Initial

Value

MASK REV Spin

MASK OVER TEMP ERROR

MASK OVER VEL ERROR

Table 7: Phase Delay Register (A.C. 111)

Bit

Name

POR Initial

Value

Most Significant Bit

Least Significant Bit

SYSTEM BUS DESCRIPTION

The system bus is designed as a data acknow-

ledge handshanking bus. At the beginning of the

bus cycle the address and chip select are de-

coded transparently and qualified with read or

write going low. On a read operation, data must

not be driven for 5nsec after read goes low to al-

low the bus to clear. Once data is driven, data ac-

knowledge is driven low to notify the processor

that data is on the bus and ready to be read. The

processor reads the data and responds by raising

read. This is an indication that the processor has

compleated the read and cycle is complete. Data

acknowledge and data must go to high im-

pedence within 20ns to clear the bus for the next

L6245

11/15

L6245 bảng dữ liệu(PDF) 11 Page - STMicroelectronics

L6245 bảng dữ liệu(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

bảng dữ liệu tải về

Link URL