L6238 datasheet(17/35 Pages) STMICROELECTRONICS

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DACs as a function of the system clock repetition

rate. Fcoarse is the system clock divided by 512,

while Ffine divides the clock by 8. This gives for

example, Coarse and Fine LSB’s of 51.3us and

800ns respectively for a system clock repetition

rate of 10MHz. Therefore the best phase jitter that

could be achieved as a function of the counter

resolution is 800ns. The dynamic range of each

counter is also shown in the table.

It can be seen that the ratio of Fine to Coarse

counts is 64. The summing amplifler divides the

Fine DAC buffer output voltage by a factor of 16.

Therefore there is a 4:1 ratio of Fine to Coarse

gain.

This results in a Speed Control Loop that is fairly

easy to compensate with excellent transient re-

sponse.

The output of the PLL Detector is fed to a gener-

al purpose. filter amplifier that is used to compen-

sate the Speed Control Loop. The filter amplifier

output stage has been carefully designed to limit

the compliance voltage to a value that tracks the

Ilim Set voltage, thus limiting the amount of over-

shoot and enhancing the transient response of

the loop.

4.5 PLL Detector Output

Figure 14 is a graph of the typical DETECTOR

OUTPUT voltage as a function of the detected

phase difference as measured on production ma-

terial. The change of the gain slope is apparent

around the zero phase difference point. With the

spindle motor at phase lock, the DETECTOR

OUTPUT voltage is typically 2.0, equivalent to the

internal Virtual Ground level.

Figure 13: Coarse/Fine DAC’s Output Graphs.

Figure 14: Vdetector Output vs Phase Error.

L6238

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