CY2210

Rev 1.0, November 25, 2006

Page 2 of 10

Pin Summary

Name

Pins

Description

1

3.3V Reference ground

4

3.3V Reference voltage supply

7, 13, 19

3.3V PCI ground

10, 16

3.3V PCI voltage supply

20, 24

3.3V AGP ground

23, 27

3.3V AGP voltage supply

29

3.3V USB ground

31

3.3V USB voltage supply

40, 44

2.5V CPU ground

43, 47

2.5V CPU voltage supply

48

2.5V CPU/2 ground

51

2.5V CPU/2 voltage supply

52

2.5V APIC ground

56

2.5V APIC voltage supply

38

Analog ground to PLL and Core

39

Analog voltage supply to PLL and Core

5

Reference crystal input

6

Reference crystal feedback

CPUCLK [0–3]

41, 42, 45, 46

CPU clock outputs

PCICLK [1–7]

9, 11, 12, 14, 15, 17, 18

PCI clock outputs, synchronously running at 33.33 MHz

PCICLK_F

8

Free running PCI clock

CPUCLK/2

49, 50

CPU/2 clock outputs, drive memory clock generator

AGPCLK [0–3]

21, 22, 25, 26

AGP clock outputs, running at 66.66 MHz

APICCLK [0–2]

53, 54, 55

APIC clock outputs, running at 16.67 MHz

REFCLK [0–1]

2, 3

Reference clock outputs, 14.318 MHz

USBCLK

30

48-MHz USB clock output

CPU_STOP

36

Active LOW input, disables CPU and AGP clocks when asserted

PCI_STOP

37

Active LOW input, disables PCI clocks when asserted

PWR_DWN

35

Active LOW input, powers down part when asserted

SPREAD

34

Active LOW input, enables spread spectrum when asserted

SEL1

33

CPU frequency select input (See Function Table)

SEL0

32

CPU frequency select input (See Function Table)

SEL133

28

CPU frequency select input (See Function Table)

Note: