Rev 1.1, February 2, 2007

Page 8 of 13

SL23EP09

AC Electrical Specifications (VDD=3.3V and 2.5V) (cont.)

Symbol

Description

Condition

Min

Typ

Max

Unit

tPLLOCK

PLL Lock Time[9]

Time from 90% of VDD to valid clocks on all the

output clocks

–

–

1.0

ms

3.3V supply, >66 MHz, <15 pF

–25

50

ps

3.3V supply, >66 MHz, <30 pF, standard drive

–

65

125

ps

3.3V supply, >66 MHz, <30 pF, high drive

–

50

100

ps

2.5V supply, >66 MHz, <15 pF, standard drive

–

35

70

ps

2.5V supply, >66 MHz, <15 pF, high drive

–

30

60

ps

2.5V supply, >66 MHz, <30 pF, high drive

–

75

150

ps

S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive

–

15

40

ps

S2:S1 = 1:0 mode, 3.3V, <15pF, high drive

–

15

40

ps

S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive

–

20

50

ps

CCJ

[2,3]

Cycle-to-cycle Jitter

S2:S1 = 1:0 mode, 2.5V, <15pF, high drive

–

20

50

ps

3.3V supply, 66–100 MHz, <15 pF

–

20

50

ps

3.3V supply, >100 MHz, <15 pF

–

15

40

ps

3.3V supply, >66 MHz, <30 pF, standard drive

–

40

80

ps

3.3V supply, >66 MHz, <30 pF, high drive

–

30

70

ps

2.5V supply, >66 MHz, <15 pF, standard drive

–

25

60

ps

2.5V supply, 66–100 MHz, <15 pF, high drive

–

25

60

ps

2.5V supply, >100 MHz, <15 pF, high drive

–

15

45

ps

S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive

–

25

60

ps

S2:S1 = 1:0 mode, 3.3V, <15pF, high drive

–

25

60

ps

S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive

–

40

80

ps

PPJ

[2,3]

Peak Period Jitter

S2:S1 = 1:0 mode, 2.5V, <15pF, high drive

–

40

80

ps

Notes:

3. Typical jitter is measured at 3.3V or 2.5V, 30 C with all outputs driven into the maximum specified load.