PRINCIPLES OF OPERATION

minimum clock frequency

The minimum clock frequency limitations result from capacitor leakage from the auto-zero and reference

capacitors. Measurement cycles as high as 10

µs are not influenced by leakage error.

rejection of 50-Hz or 60-Hz pickup

To maximize the rejection of 50-Hz or 60-Hz pickup, the clock frequency should be chosen so that an integral

multiple of 50-Hz or 60-Hz periods occur during the signal integrate phase. To achieve rejection of these signals,

some clock frequencies that can be used are:

50 Hz: 250, 166.66, 125, 100 kHz, etc.

60 Hz: 300, 200, 150, 120, 100, 40, 33.33 kHz, etc.

zero-crossing flip-flop

This flip-flop interrogates the comparator’s zero-crossing status. The interrogation is performed after the

previous clock cycle and the positive half of the ongoing clock cycle has occurred, so any comparator transients

that result from the clock pulses do not affect the detection of a zero-crossing. This procedure delays the

zero-crossing detection by one clock cycle. To eliminate the inaccuracy, which is caused by this delay, the

counter is disabled for one clock cycle at the beginning of the deintegrate phase. Therefore, when the

zero-crossing is detected one clock cycle later than the zero-crossing actually occurs, the correct number of

counts is displayed.

noise

The peak-to-peak noise around zero is approximately 15

µV (peak-to-peak value not exceeded 95% of the

time). Near full scale, this value increases to approximately 30

µV. Much of the noise originates in the auto-zero

loop, and is proportional to the ratio of the input signal to the reference.

analog and digital grounds

For high-accuracy applications, ground loops must be avoided. Return currents from digital circuits must not

be sent to the analog ground line.

power supplies

The HT7135A and TLC7135A are designed to work with

±5-V power supplies. However, 5-V operation is

possible when the input signal does not vary more than

±1.5 V from midsupply.

Rev. 00

HT7135A

TLC7135A