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ADIS16060/PCBZ bảng dữ liệu(PDF) 9 Page - Analog Devices

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ADIS16060/PCBZ bảng dữ liệu(HTML) 9 Page - Analog Devices

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ADIS16060
Rev. 0 | Page 9 of 12
THEORY OF OPERATION
The ADIS16060 operates on the principle of a resonator
gyroscope. Two polysilicon sensing structures each contain a
dither frame that is electrostatically driven to resonance. This
generates the necessary velocity element to produce a Coriolis
force while rotating. At two of the outer extremes of each frame,
orthogonal to the dither motion, are movable fingers that are
placed between fixed pickoff fingers to form a capacitive pickoff
structure that senses Coriolis motion.
The resulting signal is fed to a series of gain and demodulation
stages that produce the electrical rate signal output. The rate
signal is then converted to a digital representation of the output
on the SPI pins. The dual-sensor design provides linear acceleration
(vibration, shock) rejection. Fabricating the sensor with the signal-
conditioning electronics preserves signal integrity in noisy
environments.
The electrostatic resonator requires 14 V to 16 V for operation.
Because only 5 V is typically available in most applications, a charge
pump is included on chip. After the demodulation stage, a single-
pole, low-pass filter on the chip is used to limit high frequency
artifacts before final amplification. The frequency response is
dominated by the second low-pass filter, which is set by adding
capacitance across RATE and FILT.
ANALOG-TO-DIGITAL CONVERTER INPUT
Figure 12 shows an equivalent circuit of the input structure of
the ADIS16060 auxiliary ADC.
The two diodes, D1 and D2, provide ESD protection for the analog
inputs, AINx (AIN1 and AIN2). Care must be taken to ensure
that the analog input signal does not exceed the supply rails by
more than 0.3 V, because exceeding this level causes these diodes to
become forward-biased and to start conducting current. However,
these diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions may eventually occur
when the input signals exceed either VCC or GND.
CIN
RIN
D1
D2
CPIN
AINx
GND
VDD
Figure 12. Equivalent Analog Input Circuit
During the acquisition phase, the impedance model for AINx is a
parallel combination of the capacitor CPIN and the network formed
by the series connection of RIN and CIN. CPIN is primarily the pin
capacitance. RIN is typically 600 Ω and is a lumped component
made up of some serial resistors and the on resistance of the
switches. CIN is typically 30 pF and mainly functions as the
ADC sampling capacitor.
During the conversion phase, when the switches are open, the
input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter that reduces undesirable aliasing effects and
limits the noise.
When the source impedance of the driving circuit is low, the
ADC input can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance.
RATE SENSITIVE AXIS
1
4 5
8
LONGITUDINAL
AXIS
RATE
AXIS
POSITIVE
MEASUREMENT
DIRECTION
LATERAL
AXIS
Figure 13. Rate Signal Increases with Clockwise Rotation



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