9.4 Layout

9.4.1 Layout Guidelines

Because the LSF0102-Q1 device is a switch-type level translator, the signal integrity is dependent upon the

pull-up resistor value and PCB board parasitics. Consider the following recommendations when designing with

the LSF0102-Q1.

• Minimize the signal trace length to reduce capacitance

• Avoid using stubs in the signal path to reduce parasitics.

• Place the LSF0102-Q1 device near the high voltage side.

• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

9.4.2 Layout Example

GND

Vref_A

EN

Vref_B

A1

A2

B1

B2

LSF0102-Q1

Short Signal Trace as possible

Minimize Stub as possible

1

2

3

4

5

6

7

8

Figure 9-7. Short Trace Layout

SDIO Connector

(3.3V IO)

SD Controller

(1.8V IO)

LSF0102-Q1

SDIO level translator

Device PCB

TP1

TP2

Figure 9-8. Device Placement

LSF0102-Q1

SDLS969B – MAY 2018 – REVISED MAY 2023

www.ti.com

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