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TUSB9261 bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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TUSB9261 bảng dữ liệu(HTML) 10 Page - Texas Instruments |
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10 / 29 page ![]() SATA Gen1/2 TUSB9260 HDD USB 3.0 SuperSpeed (1) USB 2.0 High-speed (1) PC with USB 3.0 Support TUSB9261 10 TUSB9261 SLLSE67I – MARCH 2011 – REVISED MARCH 2016 www.ti.com Product Folder Links: TUSB9261 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated 7 Detailed Description 7.1 Overview The major functional blocks are as follows: • Cortex M3 microcontroller subsystem including the following peripherals: – Time interrupt modules, including watchdog timer – Universal asynchronous receive/transmit (SCI) – SPI – General purpose input/output (GPIO) – PWM for support of PWM outputs (PWM) • USB 3.0 core (endpoint controller) and integrated USB 3.0 PHY • AHCI-compliant SATA controller and integrated SATA PHY – Supporting Gen1i, Gen1m, Gen2i, and Gen2m • Chip level clock generation and distribution • Support for JTAG 1149.1 and 1149.6 7.2 Functional Block Diagram A. USB connection is made at either SuperSpeed or high speed, depending on the upstream connection support. 7.3 Feature Description 7.3.1 Operation 7.3.1.1 General Functionality The TUSB9261 ROM contains boot code that executes after a global reset, which performs the initial configuration required to load a firmware image from an attached SPI flash memory to local RAM. After the firmware is loaded, it configures the SATA advanced host controller interface host bus adapter (AHCI) and the USB device controller. In addition, the configuration of the AHCI includes a port reset, which initiates an out of band (OOB) TX sequence from the AHCI link layer to determine if a device is connected, and if so, negotiate the connection speed with the device (3.0 Gbps or 1.5 Gbps). The configuration of the USB device controller includes creation of the descriptors, configuration of the device endpoints for support of UASP and USB mass storage class BOT, allocation of memory for the transmit request blocks (TRBs), and creation of the TRBs necessary to transmit and receive packet data over the USB. In addition, the firmware provides any other custom configuration required for application-specific implementation, for example, a HID interface for user initiated backup. |
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