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HCF4031 bảng dữ liệu(PDF) 5 Page - STMicroelectronics

tên linh kiện HCF4031
Giải thích chi tiết về linh kiện  64-STAGE STATIC SHIFT REGISTER
PDF  12 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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HCF4031 bảng dữ liệu(HTML) 5 Page - STMicroelectronics

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DYNAMIC ELECTRICAL CHARACTERISTICS (T amb =25°C, CL = 50pF, RL = 200kΩ,
typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall times = 20ns)
Test Conditions
Val ue
Symbol
Parameter
V DD (V) Min.
Typ.
Max.
Unit
t PHL ,
t PL H,tPLH
Propagation Delay Time :
Clock to Q,
Clock to Q
5
250
500
ns
10
110
220
15
90
180
t PHL ,
t PL H,tPHL
Propagation Delay Time :
Clock to Q’
Clock to Q
5
190
380
ns
10
80
160
15
65
130
Clock to CLD
5
100
200
ns
10
50
100
15
40
80
t THL’,tTLH Transition Time :
(any output, except QtTHL)
5
100
200
ns
10
50
100
15
40
80
t THL
Q,
5
50
100
ns
10
25
50
15
20
40
t set u p
Data Setup Time
5
30
60
ns
10
15
30
15
10
20
t ho ld
Data Hold Time
5
30
60
ns
10
15
30
15
10
20
t W
Clock Pulse Width
5
120
240
ns
10
50
100
15
40
80
f max
Maximum Clock Input
Frequency**
52
4
MHz
10
5
10
15
6
12
t r,tf
Clock Input Rise or Fall Time*
5
1000
µs
10
1000
15
200
*
If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of
the propagation delay at 50pF and the transmiti on time of the output driving stage.
*
* Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode :
fmax =
1
(n-1) CLD prop. delay + Q prop. delay + set-up time
where n = nimber of packages
b) Not Usng Delaye Clock :
fmax =
1
propagation delay + set-up time
HCC/HCF4031B
5/12



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