ADPL12005/ADPL12006

20V, 5A/6A Fully Integrated Synchronous Buck

Converters

www.analog.com

Analog Devices | 9

Pin Configurations

TOP VIEW

3

11

10

2

1

17 FC2QFN

(3.5mm x 3.75mm)

5

7

4

8

9

ADPL12005

ADPL12006

6

EN

BST

SUP

PGND

PGND

BIAS

GND

SUP

PGND

PGND

LX

Pin Descriptions

PIN

NAME

FUNCTION

1

EN

High-Voltage-Compatible Input for Circuit Activation. If this pin is low, the part is off.

2

BST

High-Side Driver Supply. Connect a 0.1μF capacitor between LX and BST for proper operation.

3, 9

SUP

IC Supply Input. Connect a 1μF or larger ceramic capacitor in parallel with a 4.7μF cap from SUP to

PGND.

4, 5, 7, 8

PGND

Power Ground. Connect all PGND pins together.

6

LX

BUCK Switching Node. High impedance when the part is off. Connect LX to the switched side of the

appropriate inductor.

10

GND

Analog Ground

11

BIAS

1.8V Internal BIAS Supply. Connect a minimum of 2μF ceramic capacitor to PGND.

12

FB

Feedback Pin. Connect a resistor divider from OUT to FB to GND to set the output voltage.

13

OUT

Buck Regulator Output Voltage-Sense Input.

14

VEA

Internal Voltage Loop Error-Amplifier Output. Connect to VEA of the target for dual-phase operation.

Leave unconnected for single-phase operation.

15

PGOOD

Open-Drain Reset Output. External pull-up is required.

16

SYNC

SYNC. If connected to GND, Skip-mode operation is enabled under light loads. If connected to BIAS,

forced-PWM mode is enabled.

17

SYNCOUT

180° Out-of-Phase Clock Output for Multiphase Operation. Leave SYNCOUT open for single-phase

operation.