TNETV2507ANPGE datasheet(39/142 Pages) TI2

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Functional Overview

April 2004 − Revised January 2008

SPRS244J

3.5.1 External Bus Selection Register (EBSR)

The External Bus Selection Register determines the mapping of the 14 (LQFP) or 21 (BGA) address signals,

16 data signals, and 15 control signals of the external parallel port. The External Bus Selection Register is

memory-mapped at port address 0x6C00. Once the bit fields of this register are changed, the routing of the

signals takes place on the next CPU clock cycle.

The reset value of the parallel port mode bit field is determined by the state of the GPIO0 pin at reset. If GPIO0

is high at reset, the full EMIF mode is enabled and the parallel port mode bit field is set to 01. If GPIO0 is low

at reset, the HPI multiplexed mode is enabled and the parallel port mode bit field is set to 11. After reset, the

parallel port should be selected to function in either EMIF mode or HPI mode. Dynamic switching of the parallel

port, once configured, is not recommended.

CLKOUT

Disable

OSC Disable

HIDL

BKE

SR STAT

HOLD

HOLDA

CKE SEL

R/W, 0

R/W, 1

R/W, 0

CKE EN

SR CMD

Reserved

(see NOTE)

Parallel Port

Mode

R/W, 0

R, 0000

R/W, 01 if GPIO0 = 1

11 if GPIO0 = 0

LEGEND: R = Read, W = Write, n = value after reset

NOTE: These bits are Reserved and must be kept as 0000 during any writes to EBSR.

Figure 3−5. External Bus Selection Register

Table 3−5. External Bus Selection Register Bit Field Description

BITS

DESCRIPTION

CLKOUT disable.

CLKOUT disable = 0:

CLKOUT enabled

CLKOUT disable = 1:

CLKOUT disabled

Oscillator disable. Works with IDLE instruction to put the clock generation domain into IDLE mode.

OSC disable = 0:

Oscillator enabled

OSC disable = 1:

Oscillator disabled

Host mode idle bit. (Applicable only if the parallel bus is configured as EHPI.)

When the parallel bus is set to EHPI mode, the clock domain is not allowed to go to idle, so a host processor can

access the DSP internal memory. The HIDL bit works around this restriction and allows the DSP to idle the clock

domain and the EHPI. When the clock domain is in idle, a host processor will not be able to access the DSP

memory.

HIDL = 0:

Host access to DSP enabled. Idling EHPI and clock domain is not allowed.

HIDL = 1:

Idles the HPI and the clock domain upon execution of the IDLE instruction when the parallel

port mode is set to 10 or 11 selecting HPI mode. In addition, bit 4 of the Idle Control Register

must be set to 1 prior to the execution of the IDLE instruction.

Bus keeper enable.†

BKE = 0:

Bus keeper, pullups/pulldowns enabled

BKE = 1:

Bus keeper, pullups/pulldowns disabled

SDRAM self-refresh status bit.

SR STAT = 0: SDRAM self-refresh signal is not asserted.

SR STAT = 1: SDRAM self-refresh signal is asserted

† Function available when the port or pins configured as input.

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